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512MB, 1GB (x64) 200-PIN DDR SODIMM
SMALL-OUTLINE DDR SDRAM DIMM
Features
* 200-pin, small-outline, dual in-line memory module (SODIMM) * Fast data transfer rates: PC1600, PC2100, and PC2700 * Utilizes 200 MT/s, 266 MT/s, or 333 MT/s DDR SDRAM components * 512MB (64 Meg x 64), 1GB (128 Meg x 64) * VDD = VDDQ = +2.5V * VDDSPD = +2.3V to +3.6V * 2.5V I/O (SSTL_2 compatible) * Commands entered on each positive CK edge * DQS edge-aligned with data for READs; centeraligned with data for WRITEs * Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle * Bidirectional data strobe (DQS) transmitted/ received with data--i.e., source-synchronous data capture * Differential clock inputs CK and CK# * Four internal device banks for concurrent operation * Programmable burst lengths: 2, 4, or 8 * Auto precharge option * Auto Refresh and Self Refresh Modes * 7.8125s maximum average periodic refresh interval * Serial Presence Detect (SPD) with EEPROM * Programmable READ CAS latency * Gold edge contacts
MT16VDDF6464H - 512MB MT16VDDF12864H - 1GB
For the latest data sheet, please refer to the MicronaWeb site: www.micron.com/moduleds
Figure 1: 200-Pin SODIMM (MO-224)
512MB Module
1GB Module
OPTIONS
MARKING G
* Package 200-pin SODIMM (standard) 200-pin SODIMM (lead-free)1 * Frequency/CAS Latency2 167 MHz (333 MT/s) CL = 2.5 133 MHz (266 MT/s) CL = 2 133 MHz (266 MT/s) CL = 2 133 MHz (266 MT/s) CL = 2.5 100 MHz (200 MT/s) CL = 2
NOTE:
Y -335 -262
-26A -265 -202
1. Contact factory for availability of lead-free products. 2. CL = CAS (READ) latency.
Table 1:
Address Table
512MB 1GB 8K 8K (A0-A12) 4 (BA0, BA1) 64 Meg x 8 2K (A0-A9, A11) 2 (S0#, S1#) 8K 8K (A0-A12) 4 (BA0, BA1) 32 Meg x 8 1K (A0-A9) 2 (S0#, S1#)
Refresh Count Device Row Addressing Device Bank Addressing Device Configuration Device Column Addressing Module Rank Addressing
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(c)2003 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
512MB, 1GB (x64) 200-PIN DDR SODIMM
Table 2: Part Numbers and Timing Parameters
MODULE DENSITY 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 1GB 1GB 1GB 1GB 1GB 1GB 1GB 1GB 1GB 1GB CONFIGURATION 64 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 128 Meg x 64 128 Meg x 64 128 Meg x 64 128 Meg x 64 128 Meg x 64 128 Meg x 64 128 Meg x 64 128 Meg x 64 128 Meg x 64 128 Meg x 64 TRANSFER RATE 2.7 GB/s 2.7 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 1.6 GB/s 1.6 GB/s 2.7 GB/s 2.7 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 1.6 GB/s 1.6 GB/s MEMORY CLOCK/ DATA BIT RATE 6ns/333 MT/s 6ns/333 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 10ns/200 MT/s 10ns/200 MT/s 6ns/333 MT/s 6ns/333 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 10ns/200 MT/s 10ns/200 MT/s LATENCY (CL - tRCD - tRP) 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2
PART NUMBER MT16VDDF6464HG-335__ MT16VDDF6464HY-335__ MT16VDDF6464HG-262__ MT16VDDF6464HY-262__ MT16VDDF6464HG-26A__ MT16VDDF6464HY-26A__ MT16VDDF6464HG-265__ MT16VDDF6464HY-265__ MT16VDDF6464HG-202__ MT16VDDF6464HY-202__ MT16VDDF12864HG-335__ MT16VDDF12864HY-335__ MT16VDDF12864HG-262__ MT16VDDF12864HY-262__ MT16VDDF12864HG-26A__ MT16VDDF12864HY-26A__ MT16VDDF12864HG-265__ MT16VDDF12864HY-265__ MT16VDDF12864HG-202__ MT16VDDF12864HY-202__
NOTE:
All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current Revision codes. Example: MT16VDDF6464HG-265A1.
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512MB, 1GB (x64) 200-PIN DDR SODIMM
Table 3: Pin Assignment (200-Pin SODIMM Front)
51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 VDD DNU DNU VSS DNU DNU VDD DNU NC VSS DNU DNU VDD CKE1 NC A12 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 A9 VSS A7 A5 A3 A1 VDD A10 BA0 WE# S0# NC VSS DQ32 DQ33 VDD DQS4 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDDSPD NC
Table 4:
Pin Assignment (200-Pin SODIMM Back)
52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 DQ31 VDD DNU DNU VSS DNU DNU VDD DNU DNU VSS VSS VDD VDD CKE0 NC A11 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 A8 VSS A6 A4 A2 A0 VDD BA1 RAS# CAS# S1# NC VSS DQ36 DQ37 VDD DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 DQ46 DQ47 VDD CK1# CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 VSS
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 CK0# VSS DQ16 DQ17 VDD DQS2 DQ18
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS DQ20 DQ21 VDD DM2 DQ22
Figure 2: Module Layout
Front View
U1 U2 U3 U4 U5 U6
Front View
U17
U1
U2
U3
U4
U7
U17
U8
U5
U6
U7
U8
PIN 1
(all odd pins)
PIN 199
PIN 1
(all odd pins)
PIN 199
Back View
U9 U10 U11 U12 U13 U14
Back View
U9
U10
U11
U12
U15
U16
U13
U14
U15
U16
PIN 200
(all even pins)
PIN 2
PIN 200
(all even pins)
PIN 2
Indicates a VDD or VDDQ pin
Indicates a VSS pin
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512MB, 1GB (x64) 200-PIN DDR SODIMM
Table 5: Pin Descriptions
SYMBOL WE#, CAS#,RAS# CK0, CK0# CK1, CK1# TYPE Input Input DESCRIPTION Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Clock: CK, CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK, and negative edge of CK#. Output data (DQs and DQS) is referenced to the crossings of CK and CK#. Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all device banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any device bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied and until CKE is first brought HIGH. After CKE is brought HIGH, it becomes an SSTL_2 input only. Chip Selects: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. Bank Address: BA0 and BA1 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. SSTL_2 reference voltage. Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presencedetect portion of the module. Data Write Mask. DM LOW allows WRITE operation. DM HIGH blocks WRITE operation. DM lines do not affect READ operation. Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables on page 3 for more information PIN NUMBERS 118, 119, 120 35, 37, 158, 160
95, 96
CKE0, CKE1
Input
121, 122
S0#, S1#
Input
116, 117
BA0, BA1
Input
99, 100, 101, 102, 105,106, 107, 108, 109, 110, 111, 112, 115
A0-A12
Input
1, 2 195 194, 196, 198 193
VREF SCL SA0-SA2 SDA
Input Input Input Input/ Output Input
12, 26, 48, 62, 134, 148, 170, 184
DM0-DM7
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512MB, 1GB (x64) 200-PIN DDR SODIMM
Table 5: Pin Descriptions (Continued)
SYMBOL DQS0-DQS7 TYPE Input/ Output Input/ Output DESCRIPTION Data Strobe: Output with READ data, input with WRITE data. DQS is edge-aligned with READ data, centered in WRITE data. Used to capture data. Data I/Os: Data bus. Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables on page 3 for more information PIN NUMBERS 11, 25, 47, 61, 133, 147, 169, 183 5, 6, 7, 8, 13, 14, 17, 18, 19, 20, 23, 24, 29, 30, 31, 32, 41, 42, 43, 44, 49, 50, 53, 54, 55, 56, 59, 60, 65, 66, 67, 68, 127, 128, 129, 130, 135, 136, 139, 140, 141, 142, 145, 146, 151, 152, 153, 154, 163, 164, 165, 166, 171, 172, 175, 176, 177, 178, 181, 182, 187, 188, 189, 190 9, 10, 21, 22, 33, 34, 36, 45, 46, 57, 58, 69, 70, 81, 82, 92, 93, 94, 113, 114, 131, 132, 143, 144, 155, 156, 157, 167, 168, 179, 180, 191, 192 3, 4, 15, 16, 27, 28, 38, 39, 40, 51, 52, 63, 64, 75, 76, 87, 88, 90, 103, 104, 125, 126, 137, 138, 149, 150, 159, 161, 162, 173, 174, 185, 186, 200 197 85, 97, 98, 123, 124, 199 71, 72, 73, 74, 77, 78, 79, 80, 83, 84, 86, 89, 91
DQ0-DQ63
VDD
Supply
Power Supply: +2.5V 0.2V.
VSS
Supply
Ground.
VDDSPD NC DNU
Supply -- --
Serial EEPROM positive power supply: +2.3V to +3.6V No Connect: These pins should be left unconnected. Do Not Use: These pins are not connected on this module, but are assigned pins on other modules in this product family.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc.
512MB, 1GB (x64) 200-PIN DDR SODIMM
Figure 3: Functional Block Diagram - 512MB
S1# S0# DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM CS# DQS DQ DQ DQ DQ U8 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U15 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U4 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U11 DQ DQ DQ DQ DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS# DQS DQ DQ DQ DQ U6 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U9 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U2 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U13 DQ DQ DQ DQ DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS# DQS DQ DQ DQ DQ U5 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U10 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U1 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U14 DQ DQ DQ DQ DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM CS# DQS DQ DQ DQ DQ U3 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U12 DQ DQ DQ DQ DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS# DQS DQ DQ DQ DQ U7 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U16 DQ DQ DQ DQ
BA0, BA1 A0-A12 RAS# CAS# CKE0 CKE1 WE#
BA0, BA1: DDR SDRAMs A0-A12: DDR SDRAMs RAS#: DDR SDRAMs CAS#: DDR SDRAMs CKE0: DDR SDRAMs U1-U8 CKE1: DDR SDRAMs U9-U16 WE#: DDR SDRAMs
120 CK0 CK0# 120 CK1 CK1# DDR SDRAMs U4, U5, U6, U8 U9, U10, U11, U15 DDR SDRAMs U1, U2, U3, U7 U12, U13, U14, U16
CK2 CK2#
120
VDDSPD SERIAL PD SCL WP VDD SDA VREF VSS
SPD/EEPROM DDR SDRAMs DDR SDRAMs DDR SDRAMs
U17
A0 A1 A2 SA0 SA1 SA2
NOTE:
1. All resistor values are 22W unless otherwise specified. 2. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at www.micron.com/ numberguide.
DDR SDRAMs: MT46V32M8S2FD DDR SDRAMs: MT46V64M8S2FD
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc.
512MB, 1GB (x64) 200-PIN DDR SODIMM
Figure 4: Functional Block Diagram - 1GB
S1# S0# DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM CS# DQS DQ DQ DQ DQ U4 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U9 DQ DQ DQ DQ 120 CK0 CK0# 120 CK1 CK1# DM CS# DQS DQ DQ DQ DQ U3 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U10 DQ DQ DQ DQ DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS# DQS DQ DQ DQ DQ U8 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U13 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U2 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U11 DQ DQ DQ DQ DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS# DQS DQ DQ DQ DQ U7 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U14 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U1 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U12 DQ DQ DQ DQ DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM CS# DQS DQ DQ DQ DQ U6 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U15 DQ DQ DQ DQ DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS# DQS DQ DQ DQ DQ U5 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U16 DQ DQ DQ DQ
BA0, BA1 A0-A12 RAS# CAS# CKE0 CKE1 WE#
BA0, BA1: DDR SDRAMs A0-A12: DDR SDRAMs RAS#: DDR SDRAMs CAS#: DDR SDRAMs CKE0: DDR SDRAMs U1-U8 CKE1: DDR SDRAMs U9-U16 WE#: DDR SDRAMs VDDSPD VDD VREF VSS
DDR SDRAMs U1, U2, U3, U7 U12, U13, U14, U16 DDR SDRAMs U4, U5, U6, U8 U9, U10, U11, U15 SPD/EEPROM DDR SDRAMs DDR SDRAMs DDR SDRAMs
CK2 CK2# SERIAL PD SCL WP
120
U17
A0 A1 A2 SA0 SA1 SA2
SDA
NOTE:
1. All resistor values are 22W unless otherwise specified. 2. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at www.micron.com/ numberguide.
DDR SDRAMs: MT46V32M8S2FD DDR SDRAMs: MT46V64M8S2FD
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc.
512MB, 1GB (x64) 200-PIN DDR SODIMM
General Description
The MT16VDDF6464H and MT16VDDF12864H are high-speed CMOS, dynamic random-access, 512MB and 1GB memory modules organized in a x64 configuration. These modules use internally configured quadbank DRAM devices. DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM module effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is an intermittent strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. DDR SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to DDR SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1 select devices bank; A0-A12 select device row). The address bits registered coincident with the READ or WRITE command are used to select the device bank and the starting device column location for the burst access. DDR SDRAM modules provides for programmable read or write burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDR SDRAM modules, the pipelined, multibank architecture of DDR SDRAM modules allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. For more information regarding DDR SDRAM operation, refer to the 256Mb or 512Mb DDR SDRAM data sheets.
Serial Presence-Detect Operation
DDR SDRAM modules incorporate serial presencedetect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C bus using the DIMM's SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect.
Mode Register Definition
The mode register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency and an operating mode, as shown in Figure 5, Mode Register Definition Diagram, on page 9. The mode register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A12 specify the operating mode.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc.
512MB, 1GB (x64) 200-PIN DDR SODIMM
Burst Length
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 5, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration. See Note 5 of Table 6, Burst Definition Table, on page 10, for Ai values). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both read and write bursts. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Figure 5: Mode Register Definition Diagram
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 Operating Mode 0* 0* * M14 and M13 (BA1 and BA0) must be "0, 0" to select the base mode register (vs. the extended mode register).
7
6543210 CAS Latency BT Burst Length
Mode Register (Mx)
Burst Length M2 M1 M0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 M3 = 0 Reserved 2 4 8 Reserved Reserved Reserved Reserved
M3 0 1
Burst Type Sequential Interleaved
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page 10.
M6 M5 M4 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
CAS Latency Reserved Reserved 2 Reserved Reserved Reserved 2.5 Reserved
Read Latency
The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 2.5 clocks, as shown in Figure 6, CAS Latency Diagram, on page 10. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. The CAS Latency Table indicates the operating frequencies at which each CAS latency setting can be used.
M13 M12 M11 M10 M9 M8 M7 0 0 0 0 0 0 0 0 0 0 0 1 0 0 M6-M0 Valid Valid Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc.
512MB, 1GB (x64) 200-PIN DDR SODIMM
Table 6: Burst Definition Table
STARTING COLUMN ADDRESS A0 0 1 A0 0 1 0 1 A0 0 1 0 1 0 1 0 1 ORDER OF ACCESSES WITHIN A BURST TYPE = SEQUENTIAL 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 TYPE = INTERLEAVED 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
Figure 6: CAS Latency Diagram
T0 CK# CK COMMAND
READ NOP NOP NOP
T1
T2
T2n
T3
T3n
BURST LENGTH 2
CL = 2 DQS DQ T0 T1 T2 T2n T3 T3n
4
8
A2 0 0 0 0 1 1 1 1
A1 0 0 1 1 A1 0 0 1 1 0 0 1 1
CK# CK COMMAND
READ
NOP
NOP
NOP
CL = 2.5 DQS DQ
Burst Length = 4 in the cases shown Shown with nominal tAC, tDQSCK, and tDQSQ TRANSITIONING DATA DON T CARE
Operating Mode
The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A12 each set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. Although not required by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.
NOTE:
1. For a burst length of two, A1-Ai select the two-data-element block; A0 selects the first access within the block. 2. For a burst length of four, A2-Ai select the four-dataelement block; A0-A1 select the first access within the block. 3. For a burst length of eight, A3-Ai select the eight-dataelement block; A0-A2 select the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 5. i = 9 (512MB); i = 9,11 (1GB)
Table 7:
CAS Latency (CL) Table
ALLOWABLE OPERATING CLOCK FREQUENCY (MHZ)
SPEED -335 -262 -26A -265 -202
CL = 2 75 f 133 75 f 133 75 f 133 75 f 100 75 f 100
CL = 2.5 75 f 167 75 f 133 75 f 133 75 f 133 75 f 125
Extended Mode Register
The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable and output drive strength. These functions are controlled via the bits shown in Figure 7, Extended Mode Register Definition Diagram, on page 11. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and
09005aef80a646bc DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
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512MB, 1GB (x64) 200-PIN DDR SODIMM
BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/ BA1 both LOW) to reset the DLL. The extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation.
Figure 7: Extended Mode Register Definition Diagram
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 Operating Mode 01 11
4
3
2
1
0
DS DLL
Extended Mode Register (Ex)
E0 0 1 E1 0 1 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E22 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 -
DLL Enable Disable Drive Strength Normal Reduced
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued.
E1, E0 Valid -
Operating Mode Reserved Reserved
NOTE:
1. BA1 and BA0 (E14 and E13) must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register). 2. The QFC# option is not supported.
09005aef80a646bc DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
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512MB, 1GB (x64) 200-PIN DDR SODIMM
Commands
The Truth Tables below provides a general reference of available commands. For a more detailed description of commands and operations, refer to the 256Mb or 512Mb DDR SDRAM component data sheet.
Table 8:
Commands Truth Table
CS# H L L L L L L L L RAS# CAS# X H L H H H L L L X H H L L H H L L WE# X H H H L L L H L ADDR X X Bank/Row Bank/Col Bank/Col X Code X Op-Code NOTES 1 1 2 3 3 4 5 6, 7 8
CKE is HIGH for all commands shown except SELF REFRESH NAME (FUNCTION) DESELECT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER
NOTE:
1. DESELECT and NOP are functionally interchangeable. 2. BA0-BA1 provide device bank address and A0-A12 provide device row address. 3. BA0-BA1 provide device bank address; A0-A9 (512MB) or A0-A9, A11 (1GB) provide device column address; A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature. 4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts. 5. A10 LOW: BA0-BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0- BA1 are "Don't Care." 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls device row addressing; all inputs and I/Os are "Don't Care" except for CKE. 8. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A12 provide the op-code to be written to the selected mode register.
Table 9:
DM Operation Truth Table
DM L H DQS Valid X
Used to mask write data; provided coincident with the corresponding data NAME (FUNCTION) WRITE Enable WRITE Inhibit
09005aef80a646bc DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
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512MB, 1GB (x64) 200-PIN DDR SODIMM
Absolute Maximum Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operaVoltage on VDD Supply Relative to VSS. . . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on VDDQ Supply Relative to VSS . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on VREF and Inputs Relative to VSS. . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on I/O Pins Relative to VSS. . . . . . . . . . . . . -0.5V to VDDQ +0.5V tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Operating Temperature TA (ambient) . . . . . . . . . . . . . . . . . . . . .. 0C to +70C Storage Temperature (plastic) . . . . . . -55C to +150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 16W Short Circuit Output Current. . . . . . . . . . . . . . . 50mA
Table 10: DC Electrical Characteristics and Operating Conditions
Notes: 1-5, 14; notes appear on pages 20-23; 0C TA +70C PARAMETER/CONDITION Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage INPUT LEAKAGE CURRENT Any input 0V VIN VDD, VREF pin 0V VIN 1.35V (All other pins not under test = 0V) SYMBOL VDD VDDQ VREF VTT VIH(DC) VIH(DC) Command/Address, RAS#, CAS#, WE# S#, CKE, CK, CK# DM DQ, DQS MIN 2.3 2.3 0.49 VDDQ VREF - 0.04 VREF + 0.15 -0.3 -32 -16 -4 -10 -16.8 16.8 MAX 2.7 2.7 0.51 VDDQ VREF + 0.04 VDD + 0.3 VREF - 0.15 32 16 4 10 - - UNITS V V V V V V NOTES 32, 36 32, 36, 39 6, 39 7, 39 25 25
II IOZ IOH IOL
A A mA mA
47 47
OUTPUT LEAKAGE CURRENT (DQs are disabled; 0V VOUT VDDQ) OUTPUT LEVELS High Current (VOUT = VDDQ - 0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)
33, 34
Table 11: AC Input Operating Conditions
Notes: 1-5, 14; notes appear on pages 20-23; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V PARAMETER/CONDITION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage I/O Reference Voltage SYMBOL VIH(AC) VIL(AC) VREF(AC) MIN VREF + 0.310 - 0.49 VDDQ MAX - VREF - 0.310 0.49 VDDQ UNIT S V V V NOTES 12, 25, 35 12, 25, 35 6
09005aef80a646bc DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
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512MB, 1GB (x64) 200-PIN DDR SODIMM
Table 12: IDD Specifications and Conditions - 512MB
Notes: 1-5, 8, 10, 12, 48; DDR SDRAM devices only; notes appear on pages 20-23; 0C TA +70C; VDD, VDDQ = +2.5V 0.2V MAX PARAMETER/CONDITION SYM IDD0a -335 1,032 -262 1,032 -26A/265 872 -202 992 UNIT S mA NOTE S 20, 42
OPERATING CURRENT: One device bank; ActivePrecharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and
DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles
OPERATING CURRENT: One device bank; Active-ReadPrecharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once
per clock cycle
IDD1a
1,392
1,312
1,192
1,272
mA
20, 42
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN);
CKE = (LOW)
IDD2Pb
64
64
64
64
mA
21, 28, 44 45
IDLE STANDBY CURRENT: CS# = HIGH; All device banks are idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN);
CKE = LOW
IDD2Fb
800
720
720
720
mA
IDD3Pb
480
400
400
480
mA
21, 28, 44 41
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One device bank active; RC = RAS (MAX); CK = CK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle
t
t t t
IDD3Nb
960
800
800
800
mA
OPERATING CURRENT: Burst = 2; Reads; Continuous
burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT =
IDD4Ra
1,432
1,232
1,232
1,432
mA
20, 42
0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control
inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle t AUTO REFRESH BURST CURRENT: RC = tRFC (MIN) RFC = 7.8125s SELF REFRESH CURRENT: CKE 0.2V
t
IDD4Wa
1,272
1,112
1,122
1,552
mA
20
IDD5b IDD5A
b
4,080 96 64 3,272
3,760 96 64 2,832
3,760 96 64 2,832
3,920 96 64 2,952
mA mA mA mA
20, 44 24, 44 9 20, 43
OPERATING CURRENT: Four device bank interleaving READs (Burst = 4) with auto precharge, tRC = minimum
t
IDD6b IDD7a
RC allowed; tCK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands a - Value calculated as one module rank in this operating condition, and all other module ranks in IDD2p (CKE LOW) mode. b - Value calculated reflects all module ranks in this operating condition.
NOTE:
09005aef80a646bc DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
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512MB, 1GB (x64) 200-PIN DDR SODIMM
Table 13: IDD Specifications and Conditions - 1GB
Notes: 1-5, 8, 10, 12, 48; DDR SDRAM devices only; notes appear on pages 20-23; 0C TA +70C; VDD, VDDQ = +2.5V 0.2V MAX PARAMETER/CONDITION SYM -335 1,080 -262 1,080 -26A/265 960 -202 960 UNIT S mA NOTE S 20, 42
OPERATING CURRENT: One device bank; ActivePrecharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and
DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles
IDD0
OPERATING CURRENT: One device bank; Active-ReadPrecharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once
per clock cycle
IDD1
1,320
1,320
1,200
1,200
mA
20, 42
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN);
CKE = (LOW)
IDD2P
80
80
80
80
mA
21, 28, 44 45
IDLE STANDBY CURRENT: CS# = HIGH; All device banks are idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN);
CKE = LOW
IDD2F
720
720
640
640
mA
IDD3P
560
560
480
480
mA
21, 28, 44 41
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT =
IDD3N
720
720
640
640
mA
IDD4R
1,360
1,360
1,200
1,200
mA
20, 42
0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control
inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle t AUTO REFRESH BURST CURRENT: RC = tRFC (MIN)
t
IDD4W
1,280
1,280
1,120
1,120
mA
20
IDD5 IDD5A IDD6 IDD7
4,640 160 80 3,280
4,640 160 80 3,240
4,480 160 80 2,840
4,480 160 80 2,840
mA mA mA mA
20, 44 24, 44 9 20, 43
RC = 7.8125s
SELF REFRESH CURRENT: CKE 0.2V
OPERATING CURRENT: Four device bank interleaving READs (Burst = 4) with auto precharge, tRC = minimum
t
RC allowed; tCK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands a - Value calculated as one module rank in this operating condition, and all other module ranks in IDD2p (CKE LOW) mode. b - Value calculated reflects all module ranks in this operating condition.
NOTE:
09005aef80a646bc DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
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512MB, 1GB (x64) 200-PIN DDR SODIMM
Table 14: Capacitance
Note: 11; notes appear notes appear on pages 20-23 PARAMETER Input/Output Capacitance: DQ, DQS,DM Input Capacitance: Command and Address, RAS#, CAS#, WE# Input Capacitance:CK, CK#, CKE, S# SYMBOL CIO CI1 CI2 MIN 7 24 12 MAX 9 40 20 UNITS pF pF pF
Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-335, -262)
Notes: 1-5, 12-15, 29, 40; notes appear on pages 20-23; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V AC CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) Address and Control input pulse width (for each input) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge command
t t t t
-335 SYMBOL MIN
t t
-262 MIN -0.75 0.45 0.45 7.5 7.5 0.5 0.5 1.75 MAX +0.75 0.55 0.55 13 13 UNITS ns
t t
MAX +0.70 0.55 0.55 13 13
NOTES 26 26 40, 46 40, 46 23, 27 23, 27 27
AC CH CL
-0.70 0.45 0.45 6 7.5 0.45 0.45 1.75 -0.60 0.35 0.35
CK
t
CL=2.5 CL=2
t
CK (2.5)
t
CK ns ns
CK (2)
t
DH DS
ns ns ns +0.75 ns
t t
t
DIPW
DQSCK DQSH DQSL DQSS
t t t
+0.60
-0.75 0.35 0.35
t
CK 22, 23
t
DQSQ 0.75 0.20 0.20
t t
0.4 1.25 0.75 0.20 0.20 CH, CL +0.70
t t
0.5 1.25
CK ns CK CK
t
t t t
DSS HP HZ LZ
DSH
t t
CH, CL +0.75
CK ns ns ns
8 16, 37 16, 38 12 12 12 12
t t
-0.70 0.75 0.75 0.8 0.8 2.2 12
t t
-0.75 0.90 0.90 1 1 2.2 15
t t
IHF ISF
ns ns ns ns ns ns ns ns ns ns
t t
IHS ISS
t
IPW QH
MRD
t
t
QHS RAS RAP
HP - QHS 0.75 70,000
HP - QHS 0.75 120,000
22, 23 31
t t
42 18
40 15
09005aef80a646bc DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
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512MB, 1GB (x64) 200-PIN DDR SODIMM
Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-335, -262) (Continued)
Notes: 1-5, 12-15, 29, 40; notes appear on pages 20-23; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V AC CHARACTERISTICS PARAMETER ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window REFRESH to REFRESH command interval Average periodic refresh interval Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command
t t t t t t
-335 SYMBOL MIN
t t
-262 MIN 60 75 15 15 MAX UNITS ns ns ns ns 1.1 0.6
t t
MAX
NOTES 44
RC
60 72 18 18 0.9 0.4 12 0.25 0 0.4 15 1
t t
RFC RP
RCD
t
RPRE RPST RRD
1.1 0.6
0.9 0.4 15 0.25 0
CK
37
t
CK ns 18, 19 17
WPRE WPST
t
t
WPRES WR
CK ns CK ns CK ns s ns ns
t
0.6
0.4 15 1
t t
0.6
t
t
WTR NA
t
REFC REFI VTD
QH - DQSQ 70.3 7.8
QH - DQSQ 70.3 7.8
22 21 21
s
t t t t
0 75 200
0 75 200
XSNR XSRD
t
CK
09005aef80a646bc DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
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512MB, 1GB (x64) 200-PIN DDR SODIMM
Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-26A, -265, -202)
Notes: 1-5, 12-15, 29, 40; notes appear on pages 20-23; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V AC CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time CL=2.5 CL=2 DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) Address and Control input pulse width (for each input) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period
t t t t
-26A SYMBOL MIN
t t
-265 MIN -0.75 0.45 0.45 7.5 10 0.5 0.5 1.75 MAX +0.75 0.55 0.55 13 13
-202 MIN -0.8 0.45 0.45 8 10 0.6 0.6 2 MAX +0.8 0.55 0.55 13 13 UNITS ns
t t
MAX +0.75 0.55 0.55 13 13
NOTES 26 26 40, 46 40, 46 23, 27 23, 27 27
AC CH CL
-0.75 0.45 0.45 7.5 7.5 0.5 0.5 1.75
CK
t
CK (2.5) CK (2)
t
CK ns ns
DH DS
ns ns ns +0.8 ns
t t
t
DIPW
t
DQSCK -0.75 DQSH 0.35
t
+0.75
-0.75 0.35 0.35
+0.75
-0.8 0.35 0.35
CK 22, 23
DQSL
0.35 0.5 0.75 0.20 0.20
t
t
DQSQ DQSS
t t
0.5 0.75 0.20 0.20
t
0.6 0.75 0.20 0.20
t
CK ns CK CK
t
1.25
1.25
1.25
t t t
DSS HP HZ LZ
DSH
t t
CH,tCL +0.75
CH,tCL +0.75
CH,tCL +0.8
CK ns ns ns ns ns ns ns ns
8 16, 37 16, 38 12 12 12 12
t t
-0.75 0.90 .900 1 1 2.2 15
t
-0.75 0.90 0.90 1 1 2.2 15
t
-0.8 1.1 1.1 1.1 1.1 2.2 16
t
IHF ISF
t t
IHS ISS
t t t
IPW
MRD
t
ns ns ns ns ns ns ns ns ns 44 31 22, 23
QH
HP -tQHS 0.75
HP -tQHS 0.75
HP -tQHS 1
t
QHS RAS
t
t t
40 20 65 75 20 20
120,000
40 20 65 75 20 20
120,000 40 120,000 20 70 80 20 20
RAP RC
t t
RFC RP
RCD
t
09005aef80a646bc DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc.
512MB, 1GB (x64) 200-PIN DDR SODIMM
Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-26A, -265, -202) (Continued)
Notes: 1-5, 12-15, 29, 40; notes appear on pages 20-23; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V AC CHARACTERISTICS PARAMETER DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window REFRESH to REFRESH command interval Average periodic refresh interval Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command
t t t
-26A SYMBOL MIN
t
-265 MIN 0.9 0.4 15 0.25 0 MAX 1.1 0.6
-202 MIN 0.9 0.4 15 0.25 0 MAX 1.1 0.6 UNITS
t t
MAX 1.1 0.6
NOTES 37
RPRE RPST RRD
0.9 0.4 15 0.25 0 0.4 15 1
t t
CK
t
t
CK ns CK ns 18, 19 17
WPRE WPST
t
t
WPRES
t
0.6
0.4 15 1
t t
0.6
0.4 15 1
t t
0.6
t
WR
CK ns CK ns s s ns
t
WTR NA
t
REFC REFI VTD
QH - DQSQ 70.3 7.8 0
QH - DQSQ 70.3 7.8 0
QH - DQSQ 70.3 7.8 0 80
22 21 21
t t t t
XSNR XSRD
75 200
75 200
ns
t
200
CK
09005aef80a646bc DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
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512MB, 1GB (x64) 200-PIN DDR SODIMM
Notes
1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: 25C, VOUT(DC) = VDDQ/2, VOUT (peak to peak) TA = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. Command/Address input slew rate = 0.5V/ns. For -262, -26A, and -265 with slew rates 1V/ns and faster, tIS and tIH are reduced to 900ps; for -335, they are reduced to 750ps. If the slew rate is less than 0.5 V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns, while tIH remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE 0.3 x VDDQ is recognized as LOW. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). The intent of the Don't Care state after completion of the postamble is the DQS-driven signal should either be high, low, or high-Z and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions high (above VIH DC (MIN) then it must not transition low (below VIH DC) prior to tDQSH (MIN). This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute Value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multi-
12.
VTT 50 Reference Point 30pF
Output (VOUT)
13.
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed 2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed 25mV for DC error and an additional 25mV for AC noise. This measurement is to be taken at the nearest VREF bypass capacitor. 7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 8. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time at CL = 2 for -262, -26A, and -202, CL = 2.5 for-335 and -265 with the outputs open. 9. Enables on-chip refresh and address counters. 10. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 11. This parameter is sampled. VDD = +2.5V 0.2V, VDDQ = +2.5V 0.2V, VREF = VSS, f = 100 MHz, =
09005aef80a646bc DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
14.
15.
16.
17.
18.
19.
20.
20
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512MB, 1GB (x64) 200-PIN DDR SODIMM
ple of tCK that meets the maximum absolute value for tRAS. The refresh period 64ms. This equates to an average refresh rate of 7.8125s. However, an AUTO REFRESH command must be asserted at least once every 70.3s; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. The valid data window is derived by achieving other specifications: tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. Figure 8, Derating Data Valid Window, shows derating curves for duty cycles ranging between 50/50 and 45/55. Each byte lane has a corresponding DQS. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). 25. To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC). 26. JEDEC specifies CK and CK# input slew rate must be 1V/ns (2V/ns differentially). 27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If the DQ/ DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and t DH for each 100mv/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain. 28. VDD must not vary more than 4 percent if CKE is not active while any bank is active. 29. The clock is allowed up to 150ps of jitter. Each timing parameter is allowed to vary by the same amount.
21.
22.
23. 24.
Figure 8: Derating Data Valid Window
3.8 3.750 3.6 3.400 3.4 3.700
3.650
3.600
3.550 3.500 3.450 3.400 3.200 3.150 3.100 3.350 3.300
3.350
3.300 3.250
3.2
NA -335 -262/-26A/-265 @ tCK = 10ns -202 @ tCK = 10ns -262/-26A/-265 @ tCK = 7.5ns -202 @ tCK = 8ns
3.250
3.050 3.000 2.950 2.900
3.0 ns 2.8 2.6
2.500
2.463
2.425
2.388
2.4
2.350
2.313
2.275
2.238
2.200
2.163
2.2
2.125
2.0
1.8 50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 Clock Duty Cycle 47/53 46.5/54.5 46/54 45.5/55.5 45/55
09005aef80a646bc DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
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512MB, 1GB (x64) 200-PIN DDR SODIMM
30. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs, collectively during bank active. 31. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(MIN) can be satisfied prior to the internal precharge command being issued. 32. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or 2.9V, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either 300mV or 2.2V, whichever is more positive. 33. Normal Output Drive Curves: a. The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 9, Pull-Down Characteristics. b. The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 9, Pull-Down Characteristics. c. The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 10, Pull-Up Characteristics. d. The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 10, Pull-Up Characteristics. e. The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0V, and at the same voltage and temperature. f. The full variation in the ratio of the nominal pull-up to pull-down current should be unity 10 percent, for device drain-to-source voltages from 0.1V to 1.0V. The voltage levels used are derived from a minimum VDD level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. VIH overshoot: VIH (MAX) = VDDQ + 1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VDD and VDDQ must track each other. This maximum value is derived from the referenced test load. In practice, the values obtained in a typical terminated design may reflect up to 310ps less for tHZ(MAX) and the last DVW. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over t DQSCK (MIN) + tRPRE (MAX) condition. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps earlier. During Initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VDD/VDDQ are 0.0V, provided a minimum of 42W of series resistance is used between the VTT supply and the input pin. The current Micron part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option.
34.
35.
36. 37.
38. 39.
40.
Figure 9: Pull-Down Characteristics
Figure 10: Pull-Up Characteristics
09005aef80a646bc DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
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512MB, 1GB (x64) 200-PIN DDR SODIMM
41. For -265, -26A, -262 and -335, IDD3N is specified to be 35mA at 100 MHz. 42. Random addressing changing and 50 percent of data changing at every transfer. 43. Random addressing changing and 100 percent of data changing at every transfer. 44. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until t REF later. 45. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is "worst case." 46. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles. 47. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 48. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or LOW.
09005aef80a646bc DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
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SPD Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 11, Data Validity, and Figure 12, Definition of Start and Stop).
SPD Acknowledge
Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (as shwon in Figure 13, Acknowledge Response From Receiver). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode.
SPD Start Condition
All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
SPD Stop Condition
All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode.
Figure 11: Data Validity
Figure 12: Definition of Start and Stop
SCL
SCL
SDA
DATA STABLE DATA CHANGE DATA STABLE
SDA
START BIT
STOP BIT
Figure 13: Acknowledge Response From Receiver
SCL from Master 8 9
Data Output from Transmitter
Data Output from Receiver Acknowledge
09005aef80a646bc DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
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Table 17: EEPROM Device Select Code
Most significant bit (b7) is sent first. SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code DEVICE TYPE IDENTIFIER b7 1 0 b6 0 1 b5 1 1 b4 0 0 CHIP ENABLE b3 SA2 SA2 b2 SA1 SA1 b1 SA0 SA0 RW B0 RW RW
Table 18: EEPROM Operating Modes
MODE Current Address Read Random Address Read Sequential Read Byte Write Page Write RW BIT 1 0 1 1 0 0 WC VIH or VIL VIH or VIL VIH or VIL VIH or VIL VIL VIL BYTES 1 1 1 1 1 16 INITIAL SEQUENCE START, Device Select, RW = `1' START, Device Select, RW = `0', Address reSTART, Device Select, RW = `1' Similar to Current or Random Address Read START, Device Select, RW = `0' START, Device Select, RW = `0'
Figure 14: SPD EEPROM Timing Diagram
tF t LOW t HIGH tR
SCL
t SU:STA t HD:STA t HD:DAT t SU:DAT t SU:STO
SDA IN
t AA t DH t BUF
SDA OUT
UNDEFINED
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512MB, 1GB (x64) 200-PIN DDR SODIMM
Table 19: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE: IOUT = 3mA INPUT LEAKAGE CURRENT: VIN = GND to VDD OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VDD or VSS POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz SYMBOL VDDSPD VIH VIL VOL ILI ILO ISB ICC MIN 2.3 VDD 0.7 -1 - - - - - MAX 3.6 VDD + 0.5 VDD 0.3 0.4 10 10 30 2 UNITS V V V V A A A mA
Table 20: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V TO +3.6V PARAMETER/CONDITION SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time
NOTE:
SYMBOL AA BUF t DH t F t HD:DAT t HD:STA t HIGH t I t LOW t R f SCL t SU:DAT t SU:STA t SU:STO t WRC
t t
MIN 0.2 1.3 200 0 0.6 0.6
MAX 0.9
UNITS s s ns ns s s s ns s s KHz ns s s ms
NOTES 1
300
2
50 1.3 0.3 400 100 0.6 0.6 10
2
3 4
1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a reSTART condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
09005aef80a646bc DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
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512MB, 1GB (x64) 200-PIN DDR SODIMM
Table 21: Serial Presence-Detect Matrix
"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes appear on page 29 BYTE 0 1 2 3 4 5 6 7 8 9 DESCRIPTION Number of Bytes Used by Micron Total Number of Bytes in SPD Device Fundamental Memory Type Number of Rows Addresses on Assembly Number of Column Addresses on Assembly Number of Physical Ranks on DIMM Module Data With Module Data With (Continued) Moduel Voltage Interface Levels SDRAM Cycle Time, (tCK), CAS Latency = 2.5 (See note 1) ENTRY (VERSION) 128 256 SDRAM DDR 13 11, 12 2 64 0 SSTL 2.5V 6ns (-335) 7ns (-262/-26A) 7.5ns( -265) 8ns (-202) 0.7ns (-335) 0.75ns (-262/-26A/-265) 0.8ns (-202) Non-ECC 7.8s/SELF x8 Non-ECC 1 clock 2, 4, 8 4 2, 2.5 0 1 Unbuffered/Diff. Clock Fast/Concurrent AP 7.5ns (-335/-262/-26A) 10ns (-265/-202) 0.7ns (-335) 0.75ns (-262/-26A/-265) 0.8ns (-202) N/A N/A 18ns (-335) 15ns (-262) 20ns (-26A/-265/-202) 12ns (-335) 15 ns (-262/-26A/-265/-202) 18ns (-335) 15ns (-262) 20ns (-26A/-265/-202) MT16VDDF6464H MT16VDDF12864H 80 08 07 0D 0A 02 40 00 04 60 70 75 80 70 75 80 00 82 08 00 01 0E 04 0C 01 02 20 C0 75 A0 70 75 80 00 00 48 3C 50 30 3C 48 3C 50 80 08 07 0D 0B 02 40 00 04 60 70 75 80 70 75 80 00 82 08 00 01 0E 04 0C 01 02 20 C0 75 A0 70 75 80 00 00 48 3C 50 30 3C 48 3C 50
10
SDRAM Access From Clock,(tAC), CAS Latency = 2.5 Module Configuration Type Refresh Rate/Type SDRAM Device Width (Primary SDRAM) Error-checking SDRAM Data Width Minimum Clock Delay, Back-to-Back Random Column Access Burst Lengths Supported Number of Banks on SDRAM Device CAS Latencies Supported CS Latency WE Latency SDRAM Module Attributes SDRAM Device Attributes: General SDRAM Cycle Time, (tCK), CAS Latency = 2 (See note 1) SDRAM Access From CK, (tAC), CAS Latency = 2
11 12 13 14 15 16 17 18 19 20 21 22 23 24
25 26 27
SDRAM Cycle Time, (tCK), CAS Latency = 1.5 SDRAM Access From CK, (tAC), CAS Latency = 1.5 Minimum Row Precharge Time, (tRP)
28 29
Minimum Row to Row Active, (tRRD) Minimum RAS# to CAS# Delay, (tRCD)
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512MB, 1GB (x64) 200-PIN DDR SODIMM
Table 21: Serial Presence-Detect Matrix (Continued)
"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes appear on page 29 BYTE 30 DESCRIPTION Minimum RAS# Pulse Width, (tRAS) (See note 2) Module Rank Density Address and Command Setup Time, (tIS) (See note 3) Address and Command Hold Time, (tIH) (See note 3) Data/ Data Mask Input Setup Time, (tDS) ENTRY (VERSION) 42ns (-335) 45ns (-262/-26A/-265) 40ns (-202) 256MB, 512MB 0.8ns (-335) 1ns (-262/-26A/-265) 1.1ns (-202) 0.8ns (-335) 1ns (-262/-26A/-265) 1.1ns (-202) 0.45ns (-335) 0.5ns (-262/-26A/-265) 0.6ns (-202) 0.45ns (-335) 0.5ns (-262/-26A/-265) 0.6ns (-202) MT16VDDF6464H MT16VDDF12864H 2A 2D 28 40 80 A0 B0 80 A0 B0 45 50 60 45 50 60 00 3C 41 46 48 4B 50 30 34 28 32 3C 50 75 A0 00 01 00 10 30 BB E8 18 B3 2C 00 01-0C Variable Data 01-09 00 Variable Data 2A 2D 28 80 80 A0 B0 80 A0 B0 45 50 60 45 50 60 00 3C 41 46 48 4B 50 30 34 28 32 3C 50 75 A0 00 01 00 10 5F FC 29 59 F4 2C 00 01-0D Variable Data 01-09 00 Variable Data
31 32
33
34
35
Data/ Data Mask Input Hold Time, (tDH)
36-40 41
Reserved 60ns (-335/-262) 65ns (-26A/-265) 70ns (-202) 72ns (-335) Minimum Auto Refresh to Active/Auto Refresh t 75ns (-262/-26A/-265) Command Period, ( RFC) 80ns (-202) t 12ns (-335) SDRAM Device Max Cycle Time ( CKMAX) 13ns (-262/-26A/-265/-202) 0.40ns (-335) SDRAM Device Max DQS-DQ Skew Time 0.5ns (-262/-26A/-265) (tDQSQ) 0.6ns (-202) 0.5ns (-335) SDRAM Device Max Read Data Hold Skew 0.75ns (-26A/-265) Factor (tQHS) 1.0ns (-202) Reserved DIMM Height Reserved Release 1.0 SPD Revision -335 Checksum for Bytes 0-62 -262 -26A -265 -202 MICRON Manufacturer's JEDEC ID Code Manufacturer's JEDEC ID Code (Continued) 01-12 Manufacturing Location Module Part Number (ASCII) 1-9 PCB Identification Code 0 Identification Code (Continued) Year of Manufacture in BCD Minimum Active Auto Refresh Time (tRC)
42
43 44
45
46 47 48-61 62 63
64 65-71 72 73-90 91 92 93
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc.
512MB, 1GB (x64) 200-PIN DDR SODIMM
Table 21: Serial Presence-Detect Matrix (Continued)
"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes appear on page 29 BYTE 94 95-98 99-127
NOTE:
DESCRIPTION Week of Manufacture in BCD Module Serial Number Manufacturer-Specific Data (RSVD)
ENTRY (VERSION)
MT16VDDF6464H MT16VDDF12864H Variable Data Variable Data - Variable Data Variable Data -
1. Device latencies used for SPD values. 2. The value of tRAS used for -262/-26A/-265 modules is calculated from tRC - tRP. Actual device spec value is 40 ns. 3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster minimum slew rate is met.
09005aef80a646bc DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
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512MB, 1GB (x64) 200-PIN DDR SODIMM
Figure 15: 200-PIN SODIMM Dimensions - 512MB
FRONT VIEW
2.666 (67.72) 2.656 (67.45) 0.150 (3.80) MAX
0.079 (2.00) R (2X)
U1
U2
U3
U4
U5
U6
0.071 (1.80) (2X)
1.255 (31.88) 1.245 (31.62)
U7
U17
U8
0.787 (20.00) TYP
0.236 (6.00) 0.096 (2.44) 0.043 (1.10) 0.035 (0.90) 0.039 (.99) TYP 0.018 (.46) TYP 2.504 (63.60) TYP 0.024 (.61) TYP
0.079 (2.00)
PIN 199
PIN 1
BACK VIEW
U9
U10
U11
U12
U13
U14
U15
U16
PIN 200
NOTE:
PIN 2
All dimensions are in inches (millimeters) MAX or typical where noted.
MIN
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512MB, 1GB (x64) 200-PIN DDR SODIMM
Figure 16: 200-PIN SODIMM Dimensions - 1GB
FRONT VIEW
2.666 (67.72) 2.656 (67.45) 0.150 (3.80) MAX
0.079 (2.00) R (2X)
U17
U1
U2
U3
U4
0.071 (1.80) (2X)
1.255 (31.88) 1.245 (31.62)
U5 U6 U7 U8
0.787 (20.00) TYP
0.236 (6.00) 0.096 (2.44) 0.043 (1.10) 0.035 (0.90) 0.039 (.99) TYP 0.018 (.46) TYP 2.504 (63.60) TYP 0.024 (.61) TYP
0.079 (2.00)
PIN 199
PIN 1
BACK VIEW
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All dimensions are in inches (millimeters) MAX or typical where noted.
MIN
Data Sheet Designation
Released (No Mark): This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
(R)
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. All other trademarks are the property of their respective owners.
09005aef80a646bc DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN Micron Technology, Inc., reserves the right to change products or specifications without notice.. (c)2003 Micron Technology, Inc
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